-- 使用pll时钟ip核（1个10M的输入，1个25M时钟输出和1个32M时钟输出） --
-----------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity clc_one is
    port(
        reset, a : in std_logic;
        b, c : out std_logic;
        clkin : in std_logic;
        locked : out std_logic
    );
end clc_one;

architecture rtl of clc_one is
    component pll_use is
        port(
            areset : in std_logic := '0';
            inclk0 : in std_logic := '0';
            c0     : out std_logic;
            c1     : out std_logic;
            locked : out std_logic
        );
    end component pll_use;

    signal clkout0, clkout1 : std_logic;
    signal tmp : std_logic;

begin

    -- 映射
    u1: pll_use port map(
        areset => reset,
        inclk0 => clkin,
        c0 => clkout0,
        c1 => clkout1,
        locked => locked
    );

    process(clkout0, a)
    begin
        if reset = '1' then
            b <= '0';
        elsif clkout0'event and clkout0 = '1' then
            b <= not a;
            tmp <= not a;
        end if;
    end process;

    process(clkout1, a)
    begin
        if reset = '1' then
            c <= '0';
        elsif clkout1'event and clkout1 = '1' then
            c <= not tmp;
        end if;            
    end process;

end rtl;
